Developing a High Channel Count FPGA Based EGSE Architecture Utilizing COTS Hardware

Posted by Amy Larson on April 21, 2023


The development of avionics platforms for space deployment at Southwest Research Institute (SwRI) is requiring an increased need for high-speed DIO, analog channels, auxiliary electronics, and high-rate data multiplexers in a single platform. As a result, the Electrical Ground Support Equipment (EGSE) necessary to support these avionics is also gaining in complexity. 

Test hardware currently exists that will allow high-speed LVDS communication of arbitrary signals using FPGAs. 

Unfortunately, each of these test cards is only able to connect to 32 signals, making a one-to-one signal solution unfeasible. This is complicated by the fact that the wiring and cabling of such a vast number of connections to COTS test equipment will lead to signal integrity and human errors that are difficult or impossible to find.

An approach to reduce the manufacturing intensive labor was a critical consideration in the development of the new EGSE. SwRI and Circuit Check Inc. (CCI) addressed this need by simultaneously testing I/O signals that would be segmented into eight logical sections. Using five 32 channel off-the shelf FPGA cards, 48 of those channels were either multiplexed using a high speed
8-to-1 multiplexer for test system inputs or fanned out using a 1-to-8 fan out buffer for test system outputs.

A large test system interface PCBA (motherboard) was designed and manufactured that connected to the device under test on one side, with the test equipment on the other side. The high-speed splitting hardware was built on daughter cards that plugged into the motherboard. The development of a
self-test platform that performed loopback testing, was created to validate the low-level software modules, and verify that the EGSE hardware/wiring was correct. The self-test platform was a critical component in reducing the software development time by allowing SwRI to co-develop the EGSE software in parallel with the development of the avionics hardware.

The following white paper will focus on the successful approach to the development, implementation, and risk mitigation of an EGSE system for a spacecraft payload controller with more than 2500 electrical connections, including over 400 high-speed LVDS signals and another 400 low speed LVDS signals.

White paper was presented and published through IEEE Aerospace Conference in March 2023.

Click here to download the full white paper.

Topics: Test System Engineering